Linux Kernel v6.14 is Released: This is What's New for Compute Express Link (CXL)

The Linux Kernel v6.14 release brings several improvements and additions related to Compute Express Link (CXL) technology.

Release Highlights

Linux Kernel v6.14 includes 13 commits to the CXL and DAX subsystems:

The dominant story in v6.14’s CXL changes is alignment with CXL specification revision 3.1 in the event subsystem. Five event record types — Common, General Media, DRAM, Memory Module, and Component Identifier — were updated to match the latest spec. These records are how CXL devices surface hardware faults, media errors, and performance anomalies to the host, so keeping them in sync with the specification is critical for accurate error classification and interoperability with newer hardware that implements the 3.1 format changes.

On the PCI side, cxl_dvsec_rr_decode() gains support for CXL Type 1 and Type 2 devices. Previously this DVSEC range register decode path only handled Type 3 (memory-expander) devices — the class that has driven most CXL software development to date. Extending it to Type 1 (cache-coherent accelerator, no device memory) and Type 2 (accelerator with device memory) broadens the driver’s device coverage and lays groundwork for a wider range of CXL-attached accelerators and smart NICs.

The cleanup work in v6.14 shows a continued push to use generic driver core primitives rather than CXL-specific wrappers. is_cxl_nvdimm_bridge() is removed from cxl/pmem in favor of the generic device_match_type() API, and device_find_child() in the driver core is constified to improve type safety across subsystems that include CXL. A prototype correction to device_for_each_child_reverse_from() rounds out the driver core fixes.

Key Changes

• CXL 3.1 Event Record Updates: The Common, General Media, DRAM, and Memory Module event records are all updated to match CXL specification revision 3.1 field layouts. Devices implementing the newer spec will now have their reported events correctly parsed rather than silently misinterpreted.
• Component Identifier Formatting (CXL 3.1): A new Component Identifier field introduced in CXL spec 3.1 is now formatted and exposed in event output, giving operators a structured way to pinpoint which component inside a device reported an event.
• Type 1/2 Device Support in DVSEC Decode: cxl_dvsec_rr_decode() now handles CXL Type 1 (cache-coherent, no device memory) and Type 2 (with device memory) devices in addition to Type 3. This is a prerequisite for CXL-attached accelerators to participate in the driver’s range-register enumeration path.
• NVDIMM Bridge API Modernization: is_cxl_nvdimm_bridge() and the internal match_nvdimm_bridge() helper are removed from cxl/pmem, replaced by the generic device_match_type() driver core API. This reduces CXL-specific boilerplate and keeps device-matching logic in one canonical place.
• Register Block Counting Refactor: cxl/core/regs gains extracted helper functions for counting register blocks of a given type. The logic existed inline before; factoring it out makes the register enumeration code easier to test and reuse as new register block types appear in future spec revisions.
• Driver Core Const-Safety: device_find_child() is constified in the driver core and its callers — including CXL paths — are updated. This closes a category of potential const-violation bugs in code that searches the device tree without intending to modify anything.
• device_for_each_child_reverse_from() Prototype Fix: A mismatch between the function’s declaration and its actual signature is corrected. Left unfixed, this kind of prototype error can silently produce undefined behavior on architectures where the calling convention depends on argument types.

CXL related changes from Kernel v6.13 to v6.14

Here is the detailed list of all commits merged into the 6.14 Kernel for CXL and DAX. This list was generated by the Linux Kernel CXL Feature Tracker .

• Merge tag ‘cxl-for-6.14’ of git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl
• cxl/core/regs: Refactor out functions to count regblocks of given type
• cxl/events: Update Memory Module Event Record to CXL spec rev 3.1
• cxl/events: Update DRAM Event Record to CXL spec rev 3.1
• cxl/events: Update General Media Event Record to CXL spec rev 3.1
• cxl/events: Add Component Identifier formatting for CXL spec rev 3.1
• cxl/events: Update Common Event Record to CXL spec rev 3.1
• Merge 6.13-rc7 into driver-core-next
• driver core: Correct API device_for_each_child_reverse_from() prototype
• cxl/pmem: Remove is_cxl_nvdimm_bridge()
• cxl/pmem: Replace match_nvdimm_bridge() with API device_match_type()
• driver core: Constify API device_find_child() and adapt for various usages
• cxl/pci: Add CXL Type 1/2 support to cxl_dvsec_rr_decode()