Last Updated: June 2, 2026

This quick-reference guide provides a definitive, up-to-date list of generally available (GA) Compute Express Link (CXL) servers from major OEMs including Dell, HPE, Lenovo, and Supermicro. It is designed for data center architects, engineers, and IT decision-makers who need to identify and compare server platforms that support CXL 1.1 and CXL 2.0 for memory expansion and pooling.

Compute Express Link (CXL) is an open-standard interconnect that enables high-speed, low-latency communication between processors and attached devices such as accelerators and memory expanders. CXL 2.0 adoption has accelerated significantly since 2025, with all major CPU platforms now supporting it natively and the first hyperscale cloud deployments validated in production.

If you know of a GA server that should be included on this list, please let me know .

Key Terminology

• CXL (Compute Express Link): An open standard interconnect built on the PCIe physical layer that allows coherent memory sharing between a host processor and attached devices.
• GA (Generally Available): The product is officially released and can be ordered from the vendor.
• AIC (Add-In Card): A CXL device packaged in a standard PCIe card format installed in a server’s PCIe slots.
• E3.S (EDSFF 3" Short): A compact, hot-swappable form factor for CXL memory modules, designed for dense server designs.
• MRDIMM (Multiplexed Registered DIMM): A new DIMM type supported by Intel Xeon 6 offering higher memory bandwidth (up to 8800 MT/s) than standard RDIMMs.
• CXL Flat Memory Mode: An Intel Xeon 6 feature allowing the CPU to treat a mix of local DRAM and CXL-attached memory as a unified pool.

Understanding the Table Columns

CXL 2.0 Servers

CXL 2.0 introduces switching capabilities enabling memory pooling and the creation of fabric-attached memory solutions. Servers supporting CXL 2.0 are at the forefront of this architectural paradigm and are backward compatible with CXL 1.1 devices.

The dominant CXL 2.0 server generations as of mid-2026 are Intel Xeon 6 (Granite Rapids P-core and Sierra Forest E-core, released 2024) and AMD EPYC 9005 “Turin” (released 2024). Intel’s Xeon 6+ “Clearwater Forest” launched at Computex 2026 (June 2026) also carries CXL 2.0 support via 96 PCIe Gen5 lanes.

Intel Xeon 6 Platform Servers

AMD EPYC Platform Servers

CXL 1.1 Servers

CXL 1.1 focuses on memory expansion for a single host and does not support multi-host pooling or switching. These servers remain valuable for workloads requiring large memory capacity attached directly to a single CPU complex. Note that CXL 2.0 servers are backward compatible with CXL 1.1 devices—when upgrading your server infrastructure, choosing a CXL 2.0 platform future-proofs your investment.

CPU Platform CXL Support Reference

CXL support is a CPU-level feature. The server OEM can only expose what the processor’s I/O die natively implements, so understanding which generation you’re deploying is critical before specifying CXL memory or switch products.

This section covers the four processor ecosystems relevant to CXL-enabled servers as of mid-2026: Intel Xeon, AMD EPYC, Arm Neoverse, and NVIDIA Vera. Arm and NVIDIA are IP providers or new entrants rather than the OEM server vendors listed earlier in this guide, so their CXL applicability is noted where relevant.

Intel Xeon

Intel’s official CXL support matrix is documented at intel.com/content/www/us/en/support/articles/000059219 . All current Intel Xeon SKUs are browsable on the Intel ARK database .

Notes:

• All Xeon 6 generations support CXL 2.0 for Type 3 memory expansion devices (AIC and E3.S form factors).
• CXL Flat Memory Mode (Xeon 6 Granite Rapids) allows the OS to see local DDR5 and CXL-attached memory as a single pool with no special application changes.
• For the full list of Xeon 6 SKUs including core counts, TDPs, and PCIe lane counts, see Intel ARK Xeon 6 series .

AMD EPYC

AMD’s EPYC product pages are at amd.com/en/products/processors/server/epyc .

Notes on AMD CXL versioning: AMD describes EPYC 9004 (Genoa/Bergamo) as supporting CXL 1.1+ — meaning the hardware implements the CXL 1.1 specification plus a subset of CXL 2.0 features, specifically focused on Type 3 memory expansion (not multi-host pooling or switching). This is confirmed in AMD’s EPYC 9004 Memory and CXL White Paper . Full CXL 2.0 capability with switching support arrived with Turin (EPYC 9005).

Arm Neoverse

Unlike Intel and AMD, Arm does not sell CPUs directly — Arm licenses its IP to silicon partners (AWS, Ampere, NVIDIA, Qualcomm, Google, and others) who build their own server processors. Whether CXL IP blocks are instantiated in the final silicon is the implementation choice of each silicon partner, not a guarantee from Arm.

That said, Arm has included CXL support in its Neoverse IP since the N2 generation, making it available to any licensee who chooses to include it.

Real-world Neoverse CXL deployments: AWS Graviton4 is based on Neoverse V2 but does not publicly expose CXL to workloads. Ampere Altra / AmpereOne are based on Neoverse N1/N2-class architectures; CXL availability depends on each vendor’s implementation. As of mid-2026, no major hyperscaler has publicly announced Neoverse-based CXL server availability to customers.

NVIDIA Vera

NVIDIA entered the standalone CPU market with the Grace CPU (Arm Neoverse V2-based, 2023) without CXL support, and has followed with Vera, a fully custom CPU launched at GTC 2026 with commercial OEM availability expected in H2 2026.

Key point: NVIDIA Vera is the first commercially announced server CPU to implement CXL 3.1, making it the most CXL-capable CPU available as of this writing, when it ships in H2 2026. This is particularly significant for AI workloads: Vera Rubin racks expose PCIe/CXL connectors at the board edge, enabling external CXL memory pooling appliances (such as those from Liqid or H3 Platform) to attach alongside GPU resources within the same fabric.

Vera is designed primarily to run as a GPU-coupled accelerator CPU (in Vera Rubin NVL72 racks) or as a pure CPU rack (256 liquid-cooled Vera CPUs per rack). OEM server availability in single- and dual-socket configurations is expected from Cisco, Dell, HPE, Lenovo, and Supermicro in H2 2026.

What Changed Since the June 2025 Edition

New server platforms:

• HPE ProLiant DL380 Gen12 and DL380a Gen12: Full Xeon 6 refresh with CXL 2.0, up to 36 E3.S bays, up to 8 TB DDR5. Introduced 2025.
• Lenovo SR850 V4: 4-socket Xeon 6 P-core platform with CXL 2.0 and up to 16 TB of DDR5 memory. Introduced 2025.
• Lenovo SR630 V4: 1U Xeon 6 with CXL 2.0 support. Introduced 2025.
• Dell PowerEdge R6715 / R6725: AMD EPYC Turin 1U single- and dual-socket servers with CXL 2.0. GA November 2024.
• Supermicro X14 4-socket systems: CXL 2.0 ready 4-socket Intel Xeon 6 P-core systems for large-memory workloads. Shipping July 2025.
• Intel Xeon 6+ “Clearwater Forest”: Launched June 1, 2026 at Computex; available through Dell, HPE, Lenovo, and Supermicro. Up to 288 E-cores per socket on Intel 18A process. CXL 2.0 via 96 PCIe Gen5 lanes.

Deprecated / retired from CXL 2.0 table:

• The original Supermicro AS-2125HS-TNR entry (AMD Genoa / CXL 2.0) has been retained as a reference platform but is superseded by newer H13/H14 systems.

Notable real-world validation:

• Microsoft Azure M-series VMs became the first cloud service CXL deployment using Astera Labs Leo controllers (November 2025), confirming enterprise-production readiness.
• Intel and Micron demonstrated CXL E3.S expansion modules running on Xeon 6 6900P for HPC and AI workloads in production-class configurations.

Corrections from June 2025 edition:

• AMD Genoa/Bergamo CXL version corrected: The June 2025 table listed these as “CXL 2.0.” Per AMD’s own white paper, EPYC 9004 (Genoa/Bergamo) implements CXL 1.1+ — CXL 1.1 with selected Type 3 memory expansion features from the CXL 2.0 spec. Full CXL 2.0 arrived with EPYC 9005 Turin.

New CPU section added:

• A new CPU Platform CXL Support Reference section covers Intel Xeon, AMD EPYC, Arm Neoverse, and NVIDIA Vera in detail — including the important nuance that Arm licenses CXL IP to silicon partners who may or may not include it in their final designs.
• NVIDIA Vera (announced GTC 2026, OEM availability H2 2026) supports CXL 3.1 and PCIe 6.0 — the highest CXL version of any commercially announced CPU as of this writing.

Frequently Asked Questions

Q: Do I need a special CXL switch to use CXL memory on these servers? No. Every server in this list can use a CXL memory module (E3.S or AIC) connected directly to a PCIe slot, expanding that server’s local memory. A CXL switch is only required if you want to create a pool of memory shared across multiple servers.

Q: Which servers support E3.S CXL modules? Most Intel Xeon 6-based platforms include dedicated E3.S bays (typically accessed through front-accessible hot-swap slots) that can be populated with either NVMe SSDs or CXL memory modules. Check the specific server’s QVL before ordering.

Q: What memory latency penalty should I expect with CXL expansion? Approximately 70 ns of additional latency versus local DRAM. CXL memory typically appears as an additional NUMA node, so NUMA-aware applications and OS-level memory tiering (e.g., via MemVerge Memory Machine) can place workloads optimally.

Q: Are AMD EPYC Turin servers fully CXL 2.0 compatible? Yes. AMD EPYC Turin (5th Gen, EPYC 9005 series) fully supports CXL 2.0 Type 3 memory expansion via AIC slots. E3.S slot availability varies by OEM chassis design. Earlier Genoa/Bergamo platforms support CXL 1.1+ (a subset of CXL 2.0 Type 3 features) — sufficient for direct-attach memory expansion, but not full multi-host switching/pooling.

Q: When should I consider CXL 3.x servers? CXL 3.x switches are sampling now (Marvell Structera S Apollo 2, Panmnesia PANSWITCH), but the first widely available CXL 3.1 CPU platform is NVIDIA Vera (H2 2026). AMD’s upcoming EPYC “Venice” (Zen 6, TSMC 2nm) is also expected in H2 2026 and may introduce CXL 3.x support. For multi-rack pooling and Port-Based Routing, plan accordingly.

Note Always check compatability with the vendor before purchasing.