Linux Kernel v6.18 is Released: This is What's New for Compute Express Link (CXL)

Linux Kernel v6.18 is Released: This is What's New for Compute Express Link (CXL)

The Linux Kernel v6.18 release brings several improvements and additions related to Compute Express Link (CXL) technology.

Release Highlights

Linux Kernel v6.18 includes 32 commits to the CXL and DAX subsystems:

CategoryCommits
New Features & Hardware1
Bug Fixes4
Refactoring & Cleanup5
Testing2
Other20

The v6.18 kernel cycle for CXL/DAX is defined by two architectural threads running in parallel: hardening the address-translation stack and untangling port initialization from topology discovery. On the translation side, the new SPA-to-DPA region mapping infrastructure lands alongside a dedicated root-decoder ops structure that formalizes how the host physical address space is projected into CXL’s device physical address space — including XOR-interleaving math that was previously implicit. These foundations make region geometry computable and auditable in ways that earlier releases left to convention.

Port and dport lifecycle management received significant rework. Register setup for switch ports is now deferred until the first downstream port actually appears, rather than being triggered speculatively at port creation time. A matching helper to delete dports and a topology-detection helper for the root of the CXL device tree give drivers cleaner primitives to reason about partially-populated fabrics. The SSLBIS handler was simultaneously narrowed to a single-dport model, removing ambiguity in how system locality information propagates through switches.

The HMAT coupling that previously forced CXL access-coordinate updates to travel through the ACPI HMAT path is gone. CXL now writes its access coordinates directly, which removes a layering dependency and eliminates the now-dead hmat_update_target_coordinates() helper. On the observability side, poison injection gains region-level offset addressing and locked variants of the inject/clear functions, while the cxl_poison trace event correctly subtracts to recover the hpa_alias0 — fixing a latent calculation error in the tracing path.

Key Changes

  • SPA-to-DPA address translation: A new region-level mapping between System Physical Addresses and Device Physical Addresses is introduced, giving the CXL subsystem a formal, queryable translation layer rather than relying on implicit arithmetic scattered across drivers.

  • Root decoder ops and XOR math: The hpa_to_spa callback is promoted into a structured cxl_root_decoder_ops, and a dedicated callback for XOR-based interleave math is wired in. This makes non-standard interleave topologies first-class citizens in the decoder model.

  • Deferred dport and port register setup: Switch port component registers are now set up only when the first downstream port is discovered, rather than at port creation. Combined with a new dport-deletion helper, this makes hot-plug and partial-topology scenarios substantially less error-prone.

  • Direct CXL access coordinate updates: CXL no longer routes access-coordinate data through HMAT; it writes coordinates directly. This removes an ACPI layering dependency and deletes hmat_update_target_coordinates(), which had become dead code.

  • Region-level poison injection: Poison can now be injected and cleared by region offset rather than only by raw device address. Locked variants of the inject/clear functions are also added so callers that already hold the region lock do not need to drop it.

  • SSLBIS single-dport enforcement: The system-locality-based bandwidth and latency information (SSLBIS) handler is restricted to operate on a single downstream port, fixing an implicit assumption that previously allowed multi-dport ambiguity to silently produce incorrect locality data.

  • ACPI and resource fixes: cxl_acpi_set_cache_size() had an incorrect memory resource setup that could misconfigure cache-capable regions; this is corrected. The CFMW coherency restriction fields are also renamed to match the current CXL specification terminology, reducing confusion when reading ACPI CEDT tables.

  • match_region_by_range() fix: The region-range matching function was not calling region_res_match_cxl_range(), meaning region lookups could silently return incorrect results for non-trivial interleave configurations. The fix ensures the correct range-comparison helper is always used.

Here is the detailed list of all commits merged into the 6.18 Kernel for CXL and DAX. This list was generated by the Linux Kernel CXL Feature Tracker .

Your Personal Codespace: Self-Host VS Code on Any Server

Your Personal Codespace: Self-Host VS Code on Any Server

GitHub Codespaces and other cloud IDEs have revolutionized development, offering a complete VS Code environment that runs on a remote server and is accessible from any browser. It’s a game-changer for productivity and flexibility.

But what if you could have that same powerful, seamless experience on your own terms?

This guide will show you how to build your very own private Codespace, replicating the convenience of the GitHub experience on any server you control—be it a machine in your home lab, a dedicated server, or a budget-friendly cloud VM. We’ll explore two distinct paths to get you up and running with a persistent, browser-based VS Code instance on Ubuntu 24.04, complete with AI assistants like Gemini and GitHub Copilot to boost your workflow.

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Understanding STREAM: Benchmarking Memory Bandwidth for DRAM and CXL

Understanding STREAM: Benchmarking Memory Bandwidth for DRAM and CXL

In today’s Artificial Intelligence (AI), Machine Learning (ML), and high-performance computing (HPC) landscape, memory bandwidth is a critical factor in determining overall system performance. As workloads grow increasingly data-intensive, traditional DRAM-only setups are often insufficient, prompting the rise of new memory expansion technologies like Compute Express Link (CXL). To evaluate memory bandwidth across DRAM and CXL devices, we use a modified industry-standard tool called STREAM.

In this blog, we’ll explore what STREAM is, how it works, why it’s commonly used for benchmarking memory bandwidth, and how a modified version of STREAM can be used to measure performance in heterogeneous memory environments, including DRAM and CXL.

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"ipmctl show -memoryresources" returns "Error: GetMemoryResourcesInfo Failed"

"ipmctl show -memoryresources" returns "Error: GetMemoryResourcesInfo Failed"

Issue:

Running ipmctl show -memoryresources returns an error similar to the following:

# ipmctl show -memoryresources

Error: GetMemoryResourcesInfo Failed

Applies To:

  • Linux & Microsoft Windows

  • Intel Optane Persistent Memory

  • ipmctl utility

Cause:

The Platform Configuration Data (PCD) is invalid or has been erased using a previously executed ipmctl delete -dimm -pcd command or the system has new persistent memory modules that have not been initialized yet.

A module with an empty PCD will show information similar to the following. This shows an example of PCD of DIMM ID 0x0001. To review the PCD for all modules in the system use ipmctl show -dimm -pcd.

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