Linux Kernel v7.0 is Released: This is What's New for Compute Express Link (CXL)

Linux Kernel v7.0 is Released: This is What's New for Compute Express Link (CXL)

The Linux Kernel v7.0 release brings several improvements and additions related to Compute Express Link (CXL) technology.

Release Highlights

Linux Kernel v7.0 includes 73 commits to the CXL and DAX subsystems:

CategoryCommits
New Features & Hardware3
Bug Fixes11
Refactoring & Cleanup9
Testing2
Other48

Linux v7.0 brings focused but meaningful progress to the CXL/DAX subsystem, with the headline work centered on platform-specific address translation. The cxl/atl subsystem gains AMD Zen5 support through the ACPI Platform Runtime Mechanism Table (PRMT), enabling hardware-assisted Host Physical Address (HPA) to System Physical Address (SPA) translation on AMD’s latest server platforms. This required scaffolding across several layers: EFI runtime services preparation in cxl/acpi, new translation callback hooks, decoder locking for address translation paths, and explicit disabling of these handlers when Normalized Addressing is active — a sign the translation infrastructure is maturing toward multi-vendor, multi-mode support.

Stability receives serious attention in this release. Eleven bug fixes address a range of correctness issues, including a use-after-free in cxl_detach_ep() during port teardown, a deadlock in cxl_memdev_autoremove() triggered on attach failure, and a race condition around nvdimm_bus object creation during nvdimm registration. A fix to HDM decoder fallback logic prevents incorrect DVSEC-based configuration when HDM decoders are already enabled — a subtle but important correctness fix for systems where both mechanisms coexist. Region construction also sees a leak fix and improved separation between parameter setup and construction phases.

On the cleanup front, v7.0 continues consolidating the CXL PCI stack by removing now-redundant helper functions for CXL Virtual Hierarchy, Restricted CXL Host, and Endpoint handling paths that had accumulated in core/pci.c. The port subsystem moves dport removal to devres groups, and devm_cxl_add_memdev() is converted to scope-based cleanup — both reducing manual teardown logic and aligning with modern kernel resource management conventions. Treewide memory allocation modernizations (kmalloc_obj, updated default GFP_KERNEL arguments) also sweep through CXL code as part of broader kernel hygiene work.

Key Changes

  • AMD Zen5 Address Translation via ACPI PRMT: cxl/atl now supports AMD Zen5 platforms using the ACPI Platform Runtime Mechanism Table, enabling hardware-assisted HPA-to-SPA translation for CXL memory. This brings proper CXL interleaving support to AMD’s current server-class processors.

  • HPA Translation Callback Infrastructure: New callback hooks for HPA address range translation are introduced alongside decoder locking for translation paths. Normalized Addressing mode explicitly disables these handlers, establishing a clean separation between address translation modes across different platform configurations.

  • HDM Decoder DVSEC Fallback Correctness Fix: cxl/hdm was incorrectly falling back to DVSEC-based decoder configuration even when HDM decoders were already enabled and active. The fix prevents misconfigured decoder paths on systems where both mechanisms are present.

  • Port and Region Lifecycle Safety: A use-after-free of parent_port in cxl_detach_ep() and a memory leak in __construct_region() are both resolved. These fixes matter for reliable hotplug and region teardown on production systems.

  • Deadlock and Race Condition Fixes: cxl_memdev_autoremove() could deadlock when an attach operation failed mid-flight; that code path is now corrected. A separate race in nvdimm object creation — where nvdimm_bus could be freed while nvdimm objects were still being registered — is also fixed.

  • CXL PCI Stack Consolidation: Redundant helper functions for CXL VH, RCH, and Endpoint handling are removed from core/pci.c, along with a stale FIXME comment and its associated BUILD_BUG_ON. This trims dead code and simplifies the boundary between the CXL core and the PCI integration layer.

  • cxl_memdev_attach for Ordered Device Initialization: A new cxl_memdev_attach interface coordinates setup of CXL-dependent operations, giving drivers a structured hook for initialization that depends on memory device attachment completing successfully.

  • Port and Memdev Resource Management Improvements: Dport removal in cxl/port is now managed via devres groups rather than manual teardown, and devm_cxl_add_memdev() is converted to scope-based cleanup. Both changes reduce error-prone manual resource ordering in teardown paths.

Here is the detailed list of all commits merged into the 7.0 Kernel for CXL and DAX. This list was generated by the Linux Kernel CXL Feature Tracker .

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