Blog Posts

Using Linux Kernel Tiering with Compute Express Link (CXL) Memory
In this blog post, we will walk through the process of enabling the Linux Kernel Transparent Page Placement (TPP) feature with CXL memory mapped as NUMA nodes using the system-ram namespace.
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Understanding Compute Express Link (CXL) and Its Alignment with the PCIe Specifications
How CXL Uses PCIe Electricals and Transport Layers CXL utilizes the PCIe infrastructure, starting with the PCIe 5.
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A Practical Guide to Identify Compute Express Link (CXL) Devices in Your Server
In this article, we will provide four methods for identifying CXL devices in your server and how to determine which CPU socket and NUMA node each CXL device is connected.
Read MoreHow To Install a Mainline Linux Kernel in Ubuntu
By default, Ubuntu systems run with the Ubuntu kernels provided by the Ubuntu repositories.
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An Introduction to Generative Prompt Engineeering
Introduction Over the past few years, there has been a significant explosion in the use and development of large language models (LLMs).
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How To Map a CXL Endpoint to a CPU Socket in Linux
When working with CXL Type 3 Memory Expander endpoints, it’s nice to know which CPU Socket owns the root complex for the endpoint.
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Linux NUMA Distances Explained
TL;DR: The memory latency distances between a node and itself is normalized to 10 (1.
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Using Linux Kernel Memory Tiering
In this post, I’ll discuss what memory tiering is, why we need it, and how to use the memory tiering feature available in the mainline v5.
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