CXL

Linux 7.2 Seeds "Blackwell-Next": A Deep Dive into the nvgrace-gpu VFIO CXL DVSEC Change

Linux 7.2 Seeds "Blackwell-Next": A Deep Dive into the nvgrace-gpu VFIO CXL DVSEC Change

Linux 7.2’s VFIO pull request dropped a commit with a codename I hadn’t seen before: Blackwell-Next. A Phoronix post brought this to my attention - Linux 7.2 Begins Making Preparations For NVIDIA “Blackwell-Next” - which, on the face of it looks like a minor prep patch. It is — but it’s also a clean window into where NVIDIA is taking its CPU-coherent GPU stack, how CXL is quietly becoming the standard signaling interface for next-generation accelerators, and what that means if you’re building infrastructure or tooling on top of these platforms.

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Linux Kernel v7.1 is Released: This is What's New for Compute Express Link (CXL)

Linux Kernel v7.1 is Released: This is What's New for Compute Express Link (CXL)

The Linux Kernel v7.1 release brings several improvements and additions related to Compute Express Link (CXL) technology.

Release Highlights

Linux Kernel v7.1 includes 47 commits to the CXL and DAX subsystems:

CategoryCommits
New Features & Hardware1
Bug Fixes5
Refactoring & Cleanup5
Testing1
Other35

The v7.1 CXL/DAX cycle is defined by three interlocking themes: laying the groundwork for Type 2 accelerator support, hardening the DAX/HMEM subsystem against a cluster of correctness bugs, and a focused refactoring of the region layer that splits a monolithic file into purpose-specific translation units. None of these is a headline splash feature on its own, but together they represent the kind of steady, unglamorous investment that makes the subsystem reliable enough to build production systems on.

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Linux Kernel v7.0 is Released: This is What's New for Compute Express Link (CXL)

Linux Kernel v7.0 is Released: This is What's New for Compute Express Link (CXL)

The Linux Kernel v7.0 release brings several improvements and additions related to Compute Express Link (CXL) technology.

Release Highlights

Linux Kernel v7.0 includes 73 commits to the CXL and DAX subsystems:

CategoryCommits
New Features & Hardware3
Bug Fixes11
Refactoring & Cleanup9
Testing2
Other48

Linux v7.0 brings focused but meaningful progress to the CXL/DAX subsystem, with the headline work centered on platform-specific address translation. The cxl/atl subsystem gains AMD Zen5 support through the ACPI Platform Runtime Mechanism Table (PRMT), enabling hardware-assisted Host Physical Address (HPA) to System Physical Address (SPA) translation on AMD’s latest server platforms. This required scaffolding across several layers: EFI runtime services preparation in cxl/acpi, new translation callback hooks, decoder locking for address translation paths, and explicit disabling of these handlers when Normalized Addressing is active — a sign the translation infrastructure is maturing toward multi-vendor, multi-mode support.

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Linux Kernel v6.19 is Released: This is What's New for Compute Express Link (CXL)

Linux Kernel v6.19 is Released: This is What's New for Compute Express Link (CXL)

The Linux Kernel v6.19 release brings several improvements and additions related to Compute Express Link (CXL) technology.

Release Highlights

Linux Kernel v6.19 includes 31 commits to the CXL and DAX subsystems:

CategoryCommits
New Features & Hardware1
Bug Fixes4
Refactoring & Cleanup5
Testing1
Documentation2
Other18

Linux v6.19 is a measured release for the CXL/DAX subsystem — 31 commits spread across correctness fixes, code hardening, and targeted new functionality. The headline addition is extended linear cache (ELC) region support: regions can now be flagged to indicate they carry an ELC mapping, a prerequisite for properly managing CXL memory that participates in CPU-side cache hierarchies. Alongside the feature itself, the release includes adjustments to how ELC failures are reported through cxl_acpi, and the HBIW platform-data guard that was accidentally dropped has been restored.

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Linux Kernel v6.18 is Released: This is What's New for Compute Express Link (CXL)

Linux Kernel v6.18 is Released: This is What's New for Compute Express Link (CXL)

The Linux Kernel v6.18 release brings several improvements and additions related to Compute Express Link (CXL) technology.

Release Highlights

Linux Kernel v6.18 includes 32 commits to the CXL and DAX subsystems:

CategoryCommits
New Features & Hardware1
Bug Fixes4
Refactoring & Cleanup5
Testing2
Other20

The v6.18 kernel cycle for CXL/DAX is defined by two architectural threads running in parallel: hardening the address-translation stack and untangling port initialization from topology discovery. On the translation side, the new SPA-to-DPA region mapping infrastructure lands alongside a dedicated root-decoder ops structure that formalizes how the host physical address space is projected into CXL’s device physical address space — including XOR-interleaving math that was previously implicit. These foundations make region geometry computable and auditable in ways that earlier releases left to convention.

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Linux Kernel v6.17 is Released: This is What's New for Compute Express Link (CXL)

Linux Kernel v6.17 is Released: This is What's New for Compute Express Link (CXL)

The Linux Kernel v6.17 release brings several improvements and additions related to Compute Express Link (CXL) technology.

Release Highlights

Linux Kernel v6.17 includes 32 commits to the CXL and DAX subsystems:

CategoryCommits
New Features & Hardware1
Bug Fixes6
Refactoring & Cleanup3
Other22

The v6.17 cycle for CXL and DAX is a consolidation release rather than a feature-heavy one, with 32 commits that reflect the subsystem maturing around correctness, specification compliance, and architectural hygiene. The most visible theme is alignment with CXL specification revision 3.2: the Common Event Record has been updated to match the new spec, the Memory Sparing Event Record gains kernel tracing support for the first time, and additional validity checks land for corrected volatile memory error (CVME) counts in both DRAM and General Media Event Records. This work strengthens the kernel’s ability to correctly interpret and surface CXL RAS events to userspace tooling and monitoring infrastructure.

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How to Build acpidump from Source and use it to Debug Complex CXL and PCI Issues

How to Build acpidump from Source and use it to Debug Complex CXL and PCI Issues

This article is a detailed guide on how to build the latest version of the acpidump tool from its source code. While many Linux distributions, like Ubuntu, offer a packaged version of this utility, it’s often outdated. For developers and enthusiasts working with modern hardware features, particularly those related to Compute Express Link (CXL), having the most current version is essential.

Before you begin, it’s important to remove any old, conflicting versions of the tools. If you have previously installed the acpica-tools package from your distribution’s repository, you should remove it to prevent conflicts.

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Linux Kernel v6.16 is Released: This is What's New for Compute Express Link (CXL)

Linux Kernel v6.16 is Released: This is What's New for Compute Express Link (CXL)

The Linux Kernel v6.16 release brings several improvements and additions related to Compute Express Link (CXL) technology.

Release Highlights

Linux Kernel v6.16 includes 37 commits to the CXL and DAX subsystems:

CategoryCommits
New Features & Hardware2
Bug Fixes6
Refactoring & Cleanup8
Documentation3
Other18

The Linux v6.16 kernel cycle is dominated by one clear theme: hardening CXL memory device reliability and serviceability through the EDAC subsystem. Four new control features land in this release — patrol scrub, Error Check Scrub (ECS), soft Post Package Repair (PPR), and memory sparing — each exposing a distinct class of CXL 3.0 memory maintenance operations to userspace through a consistent sysfs interface. Alongside these, support for the PERFORM_MAINTENANCE command provides the underlying mechanism that drives scrub and repair operations on compliant devices. Taken together, this work moves CXL from a device class that Linux can merely enumerate and map to one where the kernel actively participates in proactive memory health management.

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CXL Memory NUMA Node Mapping with Sub-NUMA Clustering (SNC) on Linux

CXL Memory NUMA Node Mapping with Sub-NUMA Clustering (SNC) on Linux

CXL (Compute Express Link) memory devices are revolutionizing server architectures, but they also introduce new NUMA complexity, especially when advanced memory configurations, such as Sub-NUMA Clustering (SNC), are enabled. One of the most confusing issues is the mismatch between NUMA node numbers reported by CXL sysfs attributes and those used by Linux memory management tools.

This blog post walks through a real-world scenario, complete with command outputs and diagrams, to help you understand and resolve the CXL NUMA node mapping issue with SNC enabled.

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CXL Server Buyer's Guide: A Complete List of GA Platforms

CXL Server Buyer's Guide: A Complete List of GA Platforms

Last Updated: June 2, 2026

This quick-reference guide provides a definitive, up-to-date list of generally available (GA) Compute Express Link (CXL) servers from major OEMs including Dell, HPE, Lenovo, and Supermicro. It is designed for data center architects, engineers, and IT decision-makers who need to identify and compare server platforms that support CXL 1.1 and CXL 2.0 for memory expansion and pooling.

Compute Express Link (CXL) is an open-standard interconnect that enables high-speed, low-latency communication between processors and attached devices such as accelerators and memory expanders. CXL 2.0 adoption has accelerated significantly since 2025, with all major CPU platforms now supporting it natively and the first hyperscale cloud deployments validated in production.

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Linux Kernel v6.15 is Released: This is What's New for Compute Express Link (CXL)

Linux Kernel v6.15 is Released: This is What's New for Compute Express Link (CXL)

The Linux Kernel v6.15 release brings several improvements and additions related to Compute Express Link (CXL) technology.

Release Highlights

Linux Kernel v6.15 includes 55 commits to the CXL and DAX subsystems:

CategoryCommits
New Features & Hardware6
Bug Fixes4
Performance1
Refactoring & Cleanup9
Other35

The Linux v6.15 kernel marks a meaningful expansion of CXL’s userspace interface story. The headline addition is FWCTL support: CXL devices can now expose get-feature and set-feature mailbox commands to userspace through the fwctl subsystem, giving operators and tooling a standardized RPC path to query and configure device-specific feature registers without requiring bespoke kernel drivers for each capability. This is the groundwork that enables feature negotiation at the management layer — expect CXL tooling to start consuming these interfaces quickly.

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How I Created a Custom ChatGPT Trained on the CXL Specification Documents

How I Created a Custom ChatGPT Trained on the CXL Specification Documents

If you’re working with Compute Express Link (CXL) and wish you had an AI assistant trained on all the different versions of the specification—1.0, 1.1, 2.0, 3.0, 3.1… you’re in luck.

Whether you’re a CXL device vendor, a firmware engineer, a Linux Kernel developer, a memory subsystem architect, a hardware validation engineer, or even an application developer working on CXL tools and utilities, chances are you’ve had to reference the CXL spec at some point. And if you have, you already know: these documents are dense, extremely technical, and constantly evolving.

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Linux Kernel 6.14 is Released: This is What's New for Compute Express Link (CXL)

Linux Kernel 6.14 is Released: This is What's New for Compute Express Link (CXL)

The Linux Kernel 6.14 release brings several improvements and additions related to Compute Express Link (CXL) technology.

Here is the detailed list of all commits merged into the 6.14 Kernel for CXL and DAX. This list was generated by the Linux Kernel CXL Feature Tracker .

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Linux Kernel v6.14 is Released: This is What's New for Compute Express Link (CXL)

Linux Kernel v6.14 is Released: This is What's New for Compute Express Link (CXL)

The Linux Kernel v6.14 release brings several improvements and additions related to Compute Express Link (CXL) technology.

Release Highlights

Linux Kernel v6.14 includes 13 commits to the CXL and DAX subsystems:

CategoryCommits
Bug Fixes1
Refactoring & Cleanup2
Other10

The dominant story in v6.14’s CXL changes is alignment with CXL specification revision 3.1 in the event subsystem. Five event record types — Common, General Media, DRAM, Memory Module, and Component Identifier — were updated to match the latest spec. These records are how CXL devices surface hardware faults, media errors, and performance anomalies to the host, so keeping them in sync with the specification is critical for accurate error classification and interoperability with newer hardware that implements the 3.1 format changes.

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Building NDCTL Utilities from Source: A Comprehensive Guide

Building NDCTL Utilities from Source: A Comprehensive Guide

Building NDCTL with Meson on Ubuntu 24.04

The NDCTL package includes the cxl, daxctl, and ndctl utilities. It uses the Meson build system for streamlined compilation. This guide reflects the modern build process for managing NVDIMMs, CXL, and PMEM on Ubuntu 24.04.

If you do not install a more recent Kernel than the one provided by the distro, then it is not recommended to compile these utilities from source code. If you have installed a mainline Kernel, then you will likely require a newer version of these utilities that are compatible with your Kernel. See the NDCTL Releases as the Kernel support information is provided there.

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Linux Kernel 6.13 is Released: This is What's New for Compute Express Link (CXL)

Linux Kernel 6.13 is Released: This is What's New for Compute Express Link (CXL)

The Linux Kernel 6.13 release brings several improvements and additions related to Compute Express Link (CXL) technology.

Here is the detailed list of all commits merged into the 6.13 Kernel for CXL and DAX. This list was generated by the Linux Kernel CXL Feature Tracker .

CXL related changes from Kernel v6.12 to v6.13:

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Understanding STREAM: Benchmarking Memory Bandwidth for DRAM and CXL

Understanding STREAM: Benchmarking Memory Bandwidth for DRAM and CXL

In today’s Artificial Intelligence (AI), Machine Learning (ML), and high-performance computing (HPC) landscape, memory bandwidth is a critical factor in determining overall system performance. As workloads grow increasingly data-intensive, traditional DRAM-only setups are often insufficient, prompting the rise of new memory expansion technologies like Compute Express Link (CXL). To evaluate memory bandwidth across DRAM and CXL devices, we use a modified industry-standard tool called STREAM.

In this blog, we’ll explore what STREAM is, how it works, why it’s commonly used for benchmarking memory bandwidth, and how a modified version of STREAM can be used to measure performance in heterogeneous memory environments, including DRAM and CXL.

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Linux Kernel 6.10 is Released: This is What's New for Compute Express Link (CXL)

Linux Kernel 6.10 is Released: This is What's New for Compute Express Link (CXL)

The Linux Kernel 6.10 release brings several improvements and additions related to Compute Express Link (CXL) technology.

Here is the detailed list of all commits merged into the 6.10 Kernel for CXL and DAX. This list was generated by the Linux Kernel CXL Feature Tracker .

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Linux Kernel 6.9 is Released: This is What's New for Compute Express Link (CXL)

Linux Kernel 6.9 is Released: This is What's New for Compute Express Link (CXL)

The Linux Kernel 6.9 release brings several improvements and additions related to Compute Express Link (CXL) technology.

New Features

Here is a list of new features for CXL:

Here is the detailed list of all commits merged into the 6.9 Kernel for CXL and DAX. This list was generated by the Linux Kernel CXL Feature Tracker .

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Using Linux Kernel Tiering with Compute Express Link (CXL) Memory

Using Linux Kernel Tiering with Compute Express Link (CXL) Memory

In this blog post, we will walk through the process of enabling the Linux Kernel Transparent Page Placement (TPP) feature with CXL memory mapped as NUMA nodes using the system-ram namespace. This feature allows the kernel to automatically place pages in different types of memory based on their usage patterns.

Prerequisites

This guide assumes that you are using a Fedora 36 system with Kernel 5.19.13, and that your system has a Samsung CXL device installed. You can confirm the presence of the CXL device with the following command:

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Understanding Compute Express Link (CXL) and Its Alignment with the PCIe Specifications

Understanding Compute Express Link (CXL) and Its Alignment with the PCIe Specifications

How CXL Uses PCIe Electricals and Transport Layers

CXL utilizes the PCIe infrastructure, starting with the PCIe 5.0. This ensures compatibility with existing systems while introducing new features for device connectivity and memory coherency. CXL’s ability to maintain memory coherency across shared memory pools is a significant advancement, allowing for efficient resource sharing and operand movement between accelerators and target devices.

CXL builds upon the familiar foundation of PCIe, utilizing the same physical interfaces, transport layer, and electrical signaling. This shared foundation makes CXL integration with existing PCIe systems seamless. Here’s a breakdown of how it works:

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How To Map a CXL Endpoint to a CPU Socket in Linux

How To Map a CXL Endpoint to a CPU Socket in Linux

When working with CXL Type 3 Memory Expander endpoints, it’s nice to know which CPU Socket owns the root complex for the endpoint. This is very useful for memory tiering solutions where we want to keep the execution of application processes and threads ’local’ to the memory.

CXL memory expanders appear in Linux as memory-only or cpu-less NUMA Nodes. For example, NUMA nodes 2 & 3 do not have any CPUs assigned to them.

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Linux NUMA Distances Explained

Linux NUMA Distances Explained

TL;DR: The memory latency distances between a node and itself is normalized to 10 (1.0x). Every other distance is scaled relative to that 10 base value. For example, the distance between NUMA Node 0 and 1 is 21 (2.1x), meaning if node 0 accesses memory on node 1 or vice versa, the access latency will be 2.1x more than for local memory.

Introduction

Non-Uniform Memory Access (NUMA) is a multiprocessor model in which each processor is connected to dedicated memory but may access memory attached to other processors in the system. To date, we’ve commonly used DRAM for main memory, but next-gen platforms will begin offering High-Bandwidth Memory (HBM) and Compute Express Link (CXL) attached memory. Accessing remote (to the CPU) memory takes much longer than accessing local memory, and not all remote memory has the same access latency. Depending on how the memory architecture is configured, NUMA nodes can be multiple hops away with each hop adding more latency. HBM and CXL devices will appear as memory-only (CPU-less) NUMA nodes.

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How To Emulate CXL Devices using KVM and QEMU

How To Emulate CXL Devices using KVM and QEMU

What is CXL?

Compute Express Link (CXL) is an open standard for high-speed central processing unit-to-device and CPU-to-memory connections, designed for high-performance data center computers. CXL is built on the PCI Express physical and electrical interface with protocols in three areas: input/output, memory, and cache coherence.

CXL is designed to be an industry open standard interface for high-speed communications, as accelerators are increasingly used to complement CPUs in support of emerging applications such as Artificial Intelligence and Machine Learning.

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