
How To Map a CXL Endpoint to a CPU Socket in Linux
When working with CXL Type 3 Memory Expander endpoints, it’s nice to know which CPU Socket owns the root complex
When working with CXL Type 3 Memory Expander endpoints, it’s nice to know which CPU Socket owns the root complex
TL;DR: The memory latency distances between a node and itself is normalized to 10 (1.0x). Every other distance is scaled
What is CXL? Compute Express Link (CXL) is an open standard for high-speed central processing unit-to-device and CPU-to-memory connections, designed